In this blog post, we’ll explore the principles behind semiconductor miniaturization—which has driven the proliferation of SSDs and smartphones as well as advancements in the Internet of Things (IoT), artificial intelligence (AI), and autonomous vehicles—and the technologies that have been developed to overcome its limitations.
NAND Flash and the Significance of Semiconductor Miniaturization
As demand for SSDs and smartphones surges and technologies such as the Internet of Things (IoT), artificial intelligence (AI), and autonomous vehicles advance, the importance of NAND flash is growing even more. The Internet of Things refers to intelligent technologies and services that connect various objects via the internet, enabling the exchange of information between people and objects, as well as between objects themselves. NAND flash is a non-volatile semiconductor memory that can store data even when power is disconnected and allows data to be freely written and erased. In other words, NAND flash is an essential memory technology for storing data in today’s electronic devices.
Samsung Electronics has long maintained a leading position in the global NAND flash market and ranked first worldwide in terms of revenue in the first quarter of 2026. At that time, Samsung Electronics’ share of the NAND flash market was recorded at 31.6%. However, today’s NAND flash technology is not merely evolving by reducing the size of devices on a flat plane; rather, it is advancing toward higher storage density through three-dimensional structures such as V-NAND, which stacks multiple layers vertically. Starting with 24-layer V-NAND in 2013, Samsung Electronics has increased the number of stacked layers with each successive generation.
The miniaturization of semiconductor devices plays a crucial role in increasing data processing capacity and storage density by allowing more devices to be integrated onto a single chip. In particular, in today’s environment—where both fast data processing speeds and large-capacity storage are required simultaneously—the miniaturization of semiconductors and improvements in integration density are extremely important. So, what principles have made the miniaturization of semiconductor devices possible, and how can we overcome the physical limitations that arise as device sizes shrink?
How Does a MOSFET Control Current?
To explain this, let’s first examine the MOSFET, one of the basic components that make up semiconductors. The MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) began to develop in 1959 when Mohamed Atalla and Dawon Kahng at Bell Labs successfully implemented a practical metal-oxide-semiconductor field-effect transistor, and its operation was publicly demonstrated in 1960. Therefore, rather than tracing the origins of the MOSFET to Oscar Heil’s research in the 1930s, it is more accurate to trace them to the work of Atalla and Kahng.
In a MOSFET, the source and drain are the two terminals through which current flows, and the current flow between them is controlled by the voltage applied to the gate. Forming two n-type regions on a p-type semiconductor substrate creates the source and drain; when an appropriate voltage is applied to the gate, a channel—a pathway through which electrons can move between the two n-type regions—is formed. As electrons move along this channel, current flows between the source and drain. Conversely, lowering the voltage applied to the gate causes the channel to disappear, thereby reducing or stopping the flow of current.
Here, an N-type semiconductor refers to a semiconductor in which electrons are the primary charge carriers, while a P-type semiconductor refers to one in which holes are the primary charge carriers. Holes can be understood as charge carriers that occupy the spaces left vacant by electrons. When semiconductors of different types are joined, electrons and holes diffuse, resulting in the formation of an electric field at the junction that creates a region inhibiting further diffusion. By utilizing this property of semiconductors, applying a voltage to the gate allows control of the current between the source and drain.
Miniaturizing MOSFETs that operate on this principle improves semiconductor performance and power efficiency. Miniaturized MOSFETs not only allow for higher integration density on a single semiconductor chip but also reduce the length of the interconnects connecting each MOSFET. For this reason, many semiconductor companies, including Samsung Electronics, sought to make MOSFETs even smaller to increase the integration density of semiconductor products and improve performance. Initially, it was possible to reduce device size simply by refining process technology. However, as device sizes shrank to the 90-nm range, it became difficult to continue miniaturization using only the conventional planar MOSFET structure. This is because as the MOSFET becomes smaller, the distance between the source and drain decreases, causing the drain voltage to exert a greater influence on the channel. In other words, while a MOSFET is fundamentally controlled by the gate, as miniaturization progresses, the influence of the drain grows, making it difficult to control the current as intended. Consequently, semiconductor companies and researchers have been developing new structures and process technologies to overcome the limitations of miniaturization.
How can we overcome the limits of miniaturization?
The first method to consider is Silicon-on-Insulator (SOI) technology. This method involves placing an insulating layer between the silicon substrate and the device to reduce unnecessary electrical interference between them. This allows the device to be less affected by its surroundings while ensuring reliable gate control. While SOI helps improve the device’s electrical characteristics and reduce parasitic components, it requires an additional process to form the insulating layer on top of the existing structure, so there are factors to consider regarding its application areas and cost.
The second approach is the multi-gate structure. This method involves designing a single gate to control multiple sides of the channel, thereby significantly increasing the gate’s influence. While the previous method focused on reducing unwanted electrical interference, the multi-gate structure aims to allow the gate to control the channel more strongly, thereby relatively reducing the influence of the drain. FinFET is a representative technology that has advanced this structure. In a FinFET, the channel is arranged vertically like a fin, and the gate is configured to wrap around multiple sides of the channel, enabling more effective control of the channel than conventional planar MOSFETs. Subsequent advancements in semiconductor technology have moved beyond the FinFET toward the Gate-All-Around (GAA) structure, in which the gate wraps around the channel from all sides. Major semiconductor companies, including Samsung Electronics, are overcoming the electrical limitations inherent in advanced process nodes through these new transistor structures.
In addition, various methods exist to overcome the limits of miniaturization, such as improving the properties of the insulating layer beneath the gate or utilizing strain process technologies. Strain is a concept that describes how much an object stretches or shrinks relative to its original length when subjected to tensile or compressive stress. In semiconductors, strain can be utilized by applying tensile or compressive stress to silicon or channel materials to improve charge transport characteristics. Furthermore, many researchers are developing smaller, higher-performance devices by replacing silicon—the primary material used in p-type and n-type semiconductors—with other materials. One representative example is the two-dimensional material ditellurium molybdenum (MoTe₂). In 2015, researchers from the Institute for Basic Science (IBS) and Sungkyunkwan University developed a two-dimensional semiconductor device using 0.8 nm-thick MoTe₂, a material whose properties shift between semiconducting and conducting depending on temperature. At the time, the research team highlighted the potential for this material to serve as a next-generation device material capable of overcoming the miniaturization limits of silicon.
Thus, the history of the semiconductor industry—which began to develop in earnest in the mid-1900s—has been marked by a continuous drive toward miniaturization and increased integration density. This has been made possible by the relentless efforts of researchers who have sought to understand the operating principles of MOSFETs and overcome the physical limitations that arise as devices shrink through the development of new structures, materials, and process technologies. Today, with the essential need for both fast data processing speeds and the ability to store large amounts of data, research into the miniaturization and high integration of semiconductor devices remains a critical challenge. However, future semiconductor development does not simply mean reducing the size of devices. It is evolving toward enhancing performance, power efficiency, and integration density through the combined use of new transistor structures such as FinFET and GAA, new materials, and advanced packaging technologies. Continued research and development of semiconductor devices will serve as the foundation for moving beyond nanometer-scale technology to create even more sophisticated devices and usher in a new era of semiconductors.
