In this blog post, we’ll examine the structure and operating principles of 3D transistors—which were developed to overcome the limitations of planar transistors—and explore how they have enhanced semiconductor performance and power efficiency.
There is an animated sitcom called “The Jetsons,” which first aired in 1962. In the show, the main character drives a flying car. He doesn’t need to park the car in a parking lot or take an elevator to get in and out of his house—he simply enters through a window. Traffic jams are the last thing on his mind. When stuck in a traffic jam on the way home from work, everyone has probably wished they had a car like that. In the world of computers, a problem similar to traffic congestion on the road is occurring. The most fundamental component of a computer is the “transistor,” a type of semiconductor device. A computer is a machine that takes in information expressed as 0s and 1s and performs calculations (computes), and a transistor is a semiconductor device responsible for the electrical switching necessary to process this digital information. As computer performance has greatly improved today, a single semiconductor chip can now contain over a billion transistors. The idea that a 13-inch or 15-inch laptop contains billions of transistors is so staggering—setting aside concerns about traffic congestion—that one might wonder if all those components can actually fit inside. However, semiconductor companies such as Intel and AMD, along with design and manufacturing firms, have made this possible by reducing the size of transistors and increasing their integration density. They have achieved this by drastically shrinking the size of transistors and packing them tightly together. In the past, the 22-nm process was a major technological milestone; Intel introduced 3D Tri-Gate transistors on the 22-nm process in 2011 and began mass production in 2012. Since then, semiconductor processes have become even more refined, and the 3D transistor structure has evolved from FinFET to the Gate-All-Around (GAA) structure, in which the gate surrounds the channel on all sides. It has now become difficult to sustain performance improvements simply by reducing the size of individual transistors to pack more of them onto a chip. This is because as transistors get smaller, issues such as leakage current, power consumption, and electrical control become increasingly critical. It is akin to repeatedly shrinking the size of taxis to reduce traffic congestion, only to find that there is eventually not even enough space left to carry passengers. Simply reducing size to pack in more transistors is no longer a sufficient solution. Semiconductor companies turned their attention to new approaches, one of which was transforming the transistor’s structure itself from two-dimensional to three-dimensional. The idea of floating cars in the air to reduce traffic congestion has, in the world of computers, materialized as the practical technology of three-dimensional transistors.
Of course, technology that actually floats transistors in the air has not yet been developed. To understand what is meant by “making transistors three-dimensional,” it is necessary to examine the basic principles of transistors.
In conventional planar transistors, the source, gate, and drain are arranged on a flat silicon surface. The gate controls the channel between the source and drain using voltage. When an appropriate voltage is applied to the gate, a channel is formed and current flows; when the voltage is removed, the current flow is blocked. Through this electrical switching, the transistor plays a fundamental role in representing and processing 0s and 1s in digital circuits. How effectively the channel—through which current flows beneath the gate—can be controlled is a key factor determining the transistor’s performance and power efficiency. Therefore, as transistors are scaled down, it is crucial to ensure that the gate can accurately control the current in the channel even within a smaller space. However, in planar structures, continuously reducing the size of the transistor weakens the gate’s control over the channel and can exacerbate problems such as leakage current. If we think of the signal as water, this situation is similar to having to control the flow of water through a channel with only a small inlet. Just as it becomes difficult to control the flow of water as desired if the opening is too small, it becomes difficult for the gate to sufficiently control the flow of current if the transistor is too small. In terms of computers, this leads to increased power consumption and makes it difficult to maintain stable operation. If a laptop were made smaller only to have its battery drain quickly, that would not be welcome news for consumers.
To overcome these limitations, 3D transistors were developed. The FinFET, a representative structure of 3D transistors, uses a thin silicon structure—a “fin”—erected on a flat surface as its channel. Whereas a planar transistor places the gate on the surface of the silicon, a FinFET erects the channel in three dimensions and wraps the gate around multiple sides of the channel. The 3D tri-gate transistor introduced by Intel in its 22nm process is a prime example of this concept. Because the gate controls the top and both sides of the channel, it provides stronger electrical control over the channel than a planar structure. If you think of the silicon channel as a building, the gate is a device that controls the flow of current by surrounding multiple sides of the building, rather than controlling the interior from just one side. Just as a signal that previously traveled only along the ground can now utilize the building’s sides and top, it has become possible to control the flow of current across a wider surface area. Much like the flying cars we once imagined, this approach solves problems that were confined to a two-dimensional space by utilizing a three-dimensional structure.
If you understand the principle of the transistor discussed earlier, you can also understand how a 3D transistor overcomes the limitations of a planar transistor. By configuring the channel in three dimensions and allowing the gate to control multiple surfaces of the channel—without significantly increasing the transistor’s overall area—it is possible to enhance the gate’s electrical control within the same space. As a result, it becomes possible to scale down the transistor to a smaller size while still effectively controlling current, thereby achieving both high performance and low power consumption simultaneously. In particular, when the gate controls the channel over a wider area, it helps reduce leakage current and ensures stable transistor operation even at low voltages. Intel has also introduced the 3D Tri-Gate transistor as a technology capable of improving performance and energy efficiency compared to conventional planar transistors. Conversely, this means that less power is required to achieve the same level of performance. The 3D transistor has thus made it possible to pursue both performance improvements and reduced power consumption simultaneously.
The pursuit of technological advancements—such as miniaturization, high performance, and low power consumption—involves what is often referred to as “give and take.” As size decreases, it becomes more difficult to maintain performance or power efficiency, and increasing performance often leads to higher power consumption and heat generation. Generally, technological advancement can be described as a process of selecting the desired features in an appropriate balance to meet consumer demands within this trade-off, while accepting the corresponding trade-offs. However, there are special cases, such as 3D transistors, where the structure itself is innovated to improve performance across multiple aspects simultaneously. People call these changes “innovation.” While semiconductor developers have continually faced limitations in meeting consumers’ relentless demands for miniaturization and lower power consumption, they have overcome these challenges by developing new materials, structures, and manufacturing processes. Even at the moment when it seemed that semiconductor development had truly come to an end as the miniaturization of planar transistors neared its limits, the emergence of new structures like 3D transistors enabled another leap forward. As two-dimensional planar transistors continued to shrink, small computing devices like smartphones—which were once hard to imagine—became everyday items, and the advent of three-dimensional transistors made it possible to continue the trend of miniaturization and performance improvement. And semiconductor technology did not stop there. Following FinFET, the GAA (Gate-All-Around) structure—in which the gate wraps around all sides of the channel—was introduced, and Intel is currently developing RibbonFET, a GAA-based design, as the next-generation transistor structure. Furthermore, research is underway not only on creating three-dimensional transistors but also on technologies to stack multiple transistors vertically. In 2023, Intel unveiled its 3D stacked CMOS transistor technology and announced research results demonstrating how stacking transistors vertically improves area efficiency. Semiconductor technology—evolving from planar to 3D, and now to vertical stacking—continues to advance toward packing more computational power into smaller spaces while improving power efficiency. While 3D transistors have not solved all the problems facing the semiconductor industry, they have clearly opened up new possibilities by transcending the limitations of planar structures. It will be interesting to see what new products and services—ones that were previously difficult to imagine—semiconductor technology will create through future structural innovations.
